Forum Discussion
Altera_Forum
Honored Contributor
16 years agoVHDL Protected type help
Hi everyone,.. I'm new in VHDL and FPGA, sorry for my lame question. Here I have a project, and I thing I will need to use shared variable, here is the code I made : --- Quote Star...
Altera_Forum
Honored Contributor
16 years agoThen why not combine the two processes?
you can use shared variables without the protected typing: shared variable s : std_logic; then you just write to it like any other variable. At the end of the day though, quartus is still going to give you multiple driver errors. I get the feeling you're trying to write this code as code, and not thinking about the underlying hardware, which is essential for hardware design. Without the understanding of the hardware, the VHDL will be meaningless when it comes to synthesis.