Honored Contributor
Honored ContributorThanks Mr. FvM
But I think it's specified in VHDL 2008, and I have change the VHDL input to VHDL 2008 in "Setting -> Analysis & Synthesis -> VHDL input". Is Altera Quartus II really support VHDL 2008? I need those function to design somekind of clock detector system, here the explanation : --- Quote Start --- The system should be able to detect if there is clock feeded to this system and it should be able to detect if that series of clock ended. So I think this system should be able to detect both of rising and falling edge of clock input, and I manage to deal with it using 2 processes, because of I used 2 processes then I need a variable that can be accessed from both processes, and I found shared variable in VHDL 2008 This is the timing : 1. ___| | | | | | | | | | | | | | |____ -> 6 MHz clock input 2. |||||||||||||||||||||||||||||||| -> 24 Mhz FPGA global clock input 3. _________________________|___ -> Hi signal for 1 FPGA clock cycle say that this system consist of 2 inputs and 1 output, this system should know when there is signal "no 1" as input and after signal "no 1" end, the system will send out a signal "no 3". --- Quote End --- But no luck, those error message drive me nuts... That is my is my intention, thanks for helping me and sorry for my bad explanation,... How about that...?
