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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL Protected type help

Hi everyone,.. I'm new in VHDL and FPGA, sorry for my lame question. Here I have a project, and I thing I will need to use shared variable, here is the code I made : --- Quote Star...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

hmm,...

well, I need those two processes to able to write in the (shared) variable or signal, and because signal only can be drived from one process so of course I can't... :D

or maybe you have an idea regarding my design problem using only a signal? If you really have it, I really appreciate that...

Thanks... :) :)