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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL Protected type help

Hi everyone,.. I'm new in VHDL and FPGA, sorry for my lame question. Here I have a project, and I thing I will need to use shared variable, here is the code I made : --- Quote Star...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Thanks Mr. FvM

But I think it's specified in VHDL 2008, and I have change the VHDL input to VHDL 2008 in "Setting -> Analysis & Synthesis -> VHDL input". Is Altera Quartus II really support VHDL 2008?

I need those function to design somekind of clock detector system, here the explanation :

But no luck, those error message drive me nuts...

That is my is my intention, thanks for helping me and sorry for my bad explanation,...

How about that...?

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Hi,

according to your drawing the FPGA global clock (24MHz)is running all the time and you would like to detect whether the other clock (6MHz) is on or not. Is that your intention ?

Kind regards

GPK