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Honored Contributor
Honored Contributor[VHDL] 'else generate' is not supported ...
Hi All,
I'm receiving the following error during my code compilation:(vcom-1440) Language feature ELSE GENERATE STATEMENT is not supported yet gen_flr_cnt : if (tbl(i).sbit = flr_cnt or tbl(i).pbit = flr_cnt or tbl(i).ibit = flr_cnt) generate
i_flr_cnt : entity work.flr_cnt
generic map(
TRSH =>FLR_CNT_TRSH
)
port map(
clk => clk,
rstn => rstn,
clr => cnt_clr,
flr_in => bit_vec(i),
flr_out => flr_cnt_res(i)
);
else generate flr_cnt_res(i) <= '0';
end generate gen_flr_cnt; 17 Replies
Altera_ForumStandard edition or Pro? I think it may be a Pro edition only feature.
- Altera_Forum
Actually I tried this sintax in another Quartus 16 and it passed there...
Any clue? In both the file was defined as VHDL-2008 How could it be? - Altera_Forum
Well if it's saying it's not supported, you'll have to use separate generate statements.
- Altera_Forum
What quartus version are you using" - Quartus v16
I am a bit suspicious of your generate expression though. Is it really static?" - yes, all elements inside of 'if' are constants - Altera_Forum--- Quote Start --- You are ahead of vhdl standards. You can split generate into two sections: if true generate ... end generate; if false generate ... end generate; --- Quote End --- Vhdl 2008 supports if..else generate and case generate. Quartus has supported it since at least q15 http://quartushelp.altera.com/15.0/mergedprojects/hdl/vhdl/vhdl_list_2008_vhdl_support.htm
- Altera_Forum
I was under the impression that else generate had been supported for a while. What quartus version are you using.
I am a bit suspicious of your generate expression though. Is it really static? - Altera_Forum
You are ahead of vhdl standards. You can split generate into two sections:
if true generate ... end generate; if false generate ... end generate;
