VHDL and VERILOG how i can connect together.

VHDL code likes to see a component definition to tell it what the connectivity is.

So if I have a Verilog module called 'example' with a clock and reset input, and a d input and q output, then in the VHDL file in the architecture section you need:

architecture ...
   -- Verilog component
   component example
       port (
          reset : in std_logic;
          clock : in std_logic;
          d      : in std_logic;
          q      : out std_logic
      );
   end component;
   signal reset, clock, d, q : std_logic;
begin
    u1: example
    port map (
        reset => reset,
        clock => clock,
        d      => d,
        q      => q
    );
...
end architecture;

Cheers,

Dave

thanks Dave,

can you send me any link with example and tutorial

i appreciate your quick response and your help.

(is for my individual project in the final year and i'm lost:(.....

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can you send me any link with example and tutorial

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For what? I typically use Google when I have a Verilog question, and for VHDL I have a few books, eg., Ashenden, "The designers guide to VHDL".

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is for my individual project in the final year and i'm lost

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What do you actually have to do for your final project? There is really no need to mix VHDL and Verilog if you are writing your own code. If you only have a few Verilog source files and you want to use VHDL, just port them. The basic language syntax is really not that different. Alternatively, port the VHDL to Verilog/SystemVerilog. The free Altera simulator only lets you simulate one language at a time.

Are you using the Modelsim simulator for development? If not, you should be. Modelsim and Altera have plenty of tutorials.

Cheers,

Dave

I already have the verilog code for the G-sensor of my board(DE0-Nano) , when the board is rotating then the 8 led are flashing. I want to write a code that will record data (X Y Z) from the movement of the board and store the data to the 32MB memory.

I'm a little bit of VHDL user and i don't know nothing about verilog.

Thanks for your quick response Dave.

I appriciate any help of you

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I already have the verilog code for the G-sensor of my board(DE0-Nano) , when the board is rotating then the 8 led are flashing. I want to write a code that will record data (X Y Z) from the movement of the board and store the data to the 32MB memory.

I'm a little bit of VHDL user and i don't know nothing about verilog.

--- Quote End ---

Port the Verilog code to VHDL.

The G-sensor interface is probably just a finite-state-machine and control data path.

Synchronous logic: always @ (posedge clk, negedge reset_n) becomes process(clk, rstN)

Asynchronous logic:always @ (a, b, c) becomes process (a, b, c)

Asynchronous logic:assign a = b; becomes a <= b;

However, if the Verilog code is unreadable, then its pointless porting it. Just write it yourself.

Cheers,

Dave

this is a VHDL code .i want this code in Verilog but i could not do it...

library IEEE;

use IEEE.std_logic_1164.all;

use ieee.numeric_std.all;

entity PowerControl is

port (

Clk : in std_logic;

Reset : in std_logic;

ms : in std_logic

-- xbus_hw_idct enable bit

pse_m : out std_logic);

--IDCT switch and isolation control power shut off

end;

architecture rtl of PowerControl is

type state_type is (S0, S00, S01);

signal state_m,nstate_m: state_type;

signal m:std_logic;

signal c_delay_cycles_S00,n_delay_cycles_S00: natural range 0 to 2; --delay counter for mode 0

begin

seq: process (Clk,Reset,nstate_m,n_delay_cycles_S00)

begin

if Reset = '0' then

state_m<=S0;

elsif falling_edge(Clk) then

state_m<=nstate_m;

c_delay_cycles_S00<=n_delay_cycles_S00;

end if;

end process seq;

comb_m: process (ms,state_m,c_delay_cycles_S00)

begin

case state_m is

when S0 => --Starting State

n_delay_cycles_S00<=0;

m<='1';

if ms= "0" then

nstate_m<=S00;

elsif ms= "1" then

nstate_m<=S01;

else

nstate_m<=S0;

end if;

when S00 => --Mode 0 - Multiplier OFF

if ms = "1" then

n_delay_cycles_S00 <= 0;

m<='1';

nstate_m<=S01;

elsif ms= "0" then

if c_delay_cycles_S00 < 2 then

m<='1';

n_delay_cycles_S00 <= c_delay_cycles_S00 + 1;

else

m<='0';

end if;

else

m<='1';

nstate_m<=S0;

end if;

when S01 => --Mode 0 - Multiplier ON

m<='1';

if ms = "0" then

n_delay_cycles_S00 <= 1;

nstate_m<=S00;

elsif ms= "1" then

nstate_m<=S01;

else

nstate_m<=S0;

end rtl;