Altera_Forum
Honored Contributor
Honored ContributorVHDL and VERILOG how i can connect together.
How i can integrate a verilog code into an VHDL code? I have a code in verilog and i want to use it together with a vhdl code how can i do it ?
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- can you send me any link with example and tutorial --- Quote End --- For what? I typically use Google when I have a Verilog question, and for VHDL I have a few books, eg., Ashenden, "The designers guide to VHDL". --- Quote Start --- is for my individual project in the final year and i'm lost --- Quote End --- What do you actually have to do for your final project? There is really no need to mix VHDL and Verilog if you are writing your own code. If you only have a few Verilog source files and you want to use VHDL, just port them. The basic language syntax is really not that different. Alternatively, port the VHDL to Verilog/SystemVerilog. The free Altera simulator only lets you simulate one language at a time. Are you using the Modelsim simulator for development? If not, you should be. Modelsim and Altera have plenty of tutorials. Cheers, Dave
