VHDL and VERILOG how i can connect together.

VHDL code likes to see a component definition to tell it what the connectivity is.

So if I have a Verilog module called 'example' with a clock and reset input, and a d input and q output, then in the VHDL file in the architecture section you need:

architecture ...
   -- Verilog component
   component example
       port (
          reset : in std_logic;
          clock : in std_logic;
          d      : in std_logic;
          q      : out std_logic
      );
   end component;
   signal reset, clock, d, q : std_logic;
begin
    u1: example
    port map (
        reset => reset,
        clock => clock,
        d      => d,
        q      => q
    );
...
end architecture;

Cheers,

Dave