VHDL and VERILOG how i can connect together.

this is a VHDL code .i want this code in Verilog but i could not do it...

library IEEE;

use IEEE.std_logic_1164.all;

use ieee.numeric_std.all;

entity PowerControl is

port (

Clk : in std_logic;

Reset : in std_logic;

ms : in std_logic

-- xbus_hw_idct enable bit

pse_m : out std_logic);

--IDCT switch and isolation control power shut off

end;

architecture rtl of PowerControl is

type state_type is (S0, S00, S01);

signal state_m,nstate_m: state_type;

signal m:std_logic;

signal c_delay_cycles_S00,n_delay_cycles_S00: natural range 0 to 2; --delay counter for mode 0

begin

seq: process (Clk,Reset,nstate_m,n_delay_cycles_S00)

begin

if Reset = '0' then

state_m<=S0;

elsif falling_edge(Clk) then

state_m<=nstate_m;

c_delay_cycles_S00<=n_delay_cycles_S00;

end if;

end process seq;

comb_m: process (ms,state_m,c_delay_cycles_S00)

begin

case state_m is

when S0 => --Starting State

n_delay_cycles_S00<=0;

m<='1';

if ms= "0" then

nstate_m<=S00;

elsif ms= "1" then

nstate_m<=S01;

else

nstate_m<=S0;

end if;

when S00 => --Mode 0 - Multiplier OFF

if ms = "1" then

n_delay_cycles_S00 <= 0;

m<='1';

nstate_m<=S01;

elsif ms= "0" then

if c_delay_cycles_S00 < 2 then

m<='1';

n_delay_cycles_S00 <= c_delay_cycles_S00 + 1;

else

m<='0';

end if;

else

m<='1';

nstate_m<=S0;

end if;

when S01 => --Mode 0 - Multiplier ON

m<='1';

if ms = "0" then

n_delay_cycles_S00 <= 1;

nstate_m<=S00;

elsif ms= "1" then

nstate_m<=S01;

else

nstate_m<=S0;

end rtl;