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Altera_Forum
Honored Contributor
Honored ContributorVHDL and VERILOG how i can connect together.
How i can integrate a verilog code into an VHDL code? I have a code in verilog and i want to use it together with a vhdl code how can i do it ?
Altera_ForumHonored Contributor
Honored ContributorAnd remember that the basic version of Modelsim don't allow you to mix vhdl and verilog in a project. So if you need to simulate it you'd better have everything in the same language.
