Altera_Forum
Honored Contributor
Honored ContributorVHDL - FSM Design
Hello,
I've posted this on comp.lang.vhdl, but it seems to be overridden with spam these days, so I don't think anyone will see it. I'm learning about FSMs and I'm having a hard time getting my code to run correctly. I'm getting errors that say the registers for my states won't hold outside of the clock edge, and another set of errors saying that i have multiple constant drivers that can't be resolved. Does anyone think that they could help me out with this code? I've truncated the switch, the full source can be found here http://paste.org/pastebin/view/26824 Thanks MalikLIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity part1take2 is
port(
CLOCK_50 : in std_logic;
SW : in unsigned(1 downto 0);
LEDR : out unsigned(8 downto 0)
);
end part1take2;
architecture behavioral of part1take2 is
type statet is ( A, B, C, D, E, F, G, H, I );
constant FMil: integer := 50000000;
signal count : unsigned(25 downto 0);
signal CLK : std_logic;
signal cstate, nstate : statet;
signal lstate : unsigned(8 downto 0);
begin
LEDR <= lstate;
process(CLK, SW, cstate)
begin
nstate <= cstate;
LEDR <= to_unsigned(0, 9);
if(SW(0) = '1') then
nstate <= A;
else
if(rising_edge(CLK)) then
case cstate is
when A =>
lstate <= to_unsigned(000000001, 9);
if(SW(1) = '1') then
nstate <= F;
else
nstate <= B;
end if;
when B =>
lstate <= to_unsigned(000000010, 9);
if(SW(1) = '1') then
nstate <= F;
else
nstate <= C;
end if;
t--truncated
end case;
end if;
end if;
end process;
process(CLOCK_50) begin
if rising_edge(CLOCK_50) then
if(count = FMil) then
CLK <= (not CLK);
if(CLK = '1') then
cstate <= nstate;
end if;
else
count <= count + 1;
end if;
end if;
end process;
end behavioral;
