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Honored Contributor
Honored ContributorVHDL - FSM Design
Hello, I've posted this on comp.lang.vhdl, but it seems to be overridden with spam these days, so I don't think anyone will see it. I'm learning about FSMs and I'm having a hard time getting my ...
Altera_ForumHonored Contributor
Honored Contributorcstate <= nstate; <- It needs edge-triggered.
nstate decoding DOES NOT need edge trigger. So, you need at least TWO processes.
