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Altera_Forum
Honored Contributor
Honored ContributorVHDL - FSM Design
Hello, I've posted this on comp.lang.vhdl, but it seems to be overridden with spam these days, so I don't think anyone will see it. I'm learning about FSMs and I'm having a hard time getting my ...
Altera_ForumHonored Contributor
Honored Contributorwhat in the world just happened!? you mean to tell me that double quotes could make all the difference?? VHDL can be so cruel sometimes!! :/
someone please enlighten me. :( -edit- some associates just laughed at me and explained that "x" is bit vector and to_unsigned(x,x) is integer
