VHDL - FSM Design

hello,

Thanks I did notice those mistakes and changed them, but my code still runs weird.

I'm trying to figure out the problem now.

I'm trying to learn how to use signal tap. Maybe that can tell me something about what's going on.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity part1take2 is
	port( 
		CLOCK_50	: in std_logic;
		SW			: in unsigned(1 downto 0);
		LEDR		: out unsigned(16 downto 0)
	);
end part1take2;
architecture behavioral of part1take2 is 
	
	type statet is ( A, B, C, D, E, F, G, H, I );
	constant FMil: integer := 50000000;
	
	signal count	: unsigned(25 downto 0);
	signal CLK		: std_logic;
	signal cstate, nstate : statet;
	signal led	: unsigned(8 downto 0);
	signal cled : unsigned(7 downto 0);
begin
	
	LEDR(8 downto 0) <= led;
	LEDR(16 downto 9) <= cled;
	
	process(SW, cstate) 
	begin
		
		if(SW(0) = '1') then
			nstate <= A;
		else 
			case cstate is
				when A =>
					led <= to_unsigned(000000001, 9);
					if(SW(1) = '1') then
						nstate <= F;
					else
						nstate <= B;
					end if;
				when B =>
					led <= to_unsigned(000000010, 9);
					if(SW(1) = '1') then
						nstate <= F;
					else
						nstate <= C;
					end if;
				when C =>
					led <= to_unsigned(000000100, 9);
					if(SW(1) = '1') then
						nstate <= F;
					else
						nstate <= D;
					end if;
				when D =>
					led <= to_unsigned(000001000, 9);
					if(SW(1) = '1') then
						nstate <= F;
					else
						nstate <= E;
					end if;
				when E =>
					led <= to_unsigned(000010000, 9);
					if(SW(1) = '1') then
						nstate <= F;
					else
						nstate <= E;
					end if;
				when F =>
					led <= to_unsigned(000100000, 9);
					if(SW(1) = '1') then
						nstate <= G;
					else
						nstate <= B;
					end if;
				when G =>
					led <= to_unsigned(001000000, 9);
					if(SW(1) = '1') then
						nstate <= H;
					else
						nstate <= B;
					end if;
				when H =>
					led <= to_unsigned(010000000, 9);
					if(SW(1) = '1') then
						nstate <= I;
					else
						nstate <= B;
					end if;
				when I =>
					led <= to_unsigned(100000000, 9);
					if(SW(1) = '1') then
						nstate <= I;
					else
						nstate <= B;
					end if;
			end case;
		end if;
	end process;
	
	process(CLOCK_50) begin
		if rising_edge(CLOCK_50) then
			count <= count + 1;
			cled <= cled + 1;
			if(count = FMil) then
				CLK <= (not CLK);
				if(CLK = '1') then
					cstate <= nstate;
				end if;
			end if;
		end if;
	
	end process;
	
end behavioral;