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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL - FSM Design

Hello, I've posted this on comp.lang.vhdl, but it seems to be overridden with spam these days, so I don't think anyone will see it. I'm learning about FSMs and I'm having a hard time getting my ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

decide about LEDR: is it assigned lstate or 9 ???

follow the clk temp;late below.

your clocking is not healthy even if you get no errors. 


LEDR <= lstate;
 
 process(CLK, SW, cstate) 
 begin
  
  --nstate <= cstate;
  --LEDR <= to_unsigned(0, 9);
if(SW(0) = '1') then
   nstate <= A;
  elsif(rising_edge(CLK)) then
    case cstate is...
comment out the extra end if; at end