VHDL - CASE related question

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Thank you very mcuh Tricky, mmTsuchi.

Looks like a have long way to go.

One thing that I can't understand is,

A GENERATE block and a PROCESS block, 'how many' instructions can a FPGA perform? It ofcourse depends on the model, but as a programmer, how would you know that a block of code can be executed within a clock cycle? Or is it not like that? Is possible for a block of PROCESS to take several clock cycles to execute completely?

Thank you.

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an FPGA has no instructions, only logic gates and registers, so thats not a correct question to ask. You could write a CPU using VHDL and then you could ask your question about your CPU, not the FPGA.

A clocked Process will ALWAYS complete all code lines in a single clock cycle (assuming the FPGA can meet timing requirements), but thats may not be what you understand.

for example:

signal a, b : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    a <= input
    b <= a;
    output <= b;
  end if;
end process;

The code inside the process executes on every single clock cycle. The process discribed 3 registers connected. So it would take 3 clock cycles to get the input to the output. This is a 3 stage register pipeline.

The output would produce a new value every single clock cycle, delayed by 3 clocks.

I could put a generate block around this process like this:

multi_pipeline_gen : for i in 0 to 3 generate
  --put process from before here
end generate multi_pipeline_gen;

and you get 4 parallel pipelines. Basically a process describes one bit of hardware, a generate tells you to replicated that hardware n times.

It sounds like you dont have a great understanding of digital electronics. Forget about VHDL for now and go and read up about digital logic.

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an FPGA has no instructions, only logic gates and registers, so thats not a correct question to ask. You could write a CPU using VHDL and then you could ask your question about your CPU, not the FPGA.

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Thank you Tricky!

I get that now. When you compile it will create whatever we want in digital logic. So as long as there are enough of those parts I can do any amount of assignments inside. Thank you very much.

Yes I do have a long way to go before I really start coding. Thank you for the help Tricky.

I should add that

you will learn by (good) VHDL examples and tutorials on the web (Altera and others).

They represent many "basic" VHDL codes that you can understand very well.

port type in entities :

only std_logic(_vector) : Yes, conversions are annoying but more re-usable. I think about "design re-use".

I will study that question : I have wanted to keep a certain rigor in VHDL designing. Thanks for your opinion.

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port type in entities :

only std_logic(_vector) : Yes, conversions are annoying but more re-usable. I think about "design re-use".

I will study that question : I have wanted to keep a certain rigor in VHDL designing. Thanks for your opinion.

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With Quartus (and other tools) supporting other things other than std_logic there is no reason to write what you mean. Doing all the type conversions just kills the whole point of types in VHDL, which are there for code readability. Adding in coversions all over the place makes the code more obscure.

You are right.

I began writing with other types (you had said) for port. And I finally adopt this method.

This is less obscure, simpler to "debug"....

Thanks