Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

VHDL - CASE related question

Hello, This is probably a very fundamental question but I'm a little confused as I am new to this. In VHDL (I'm sure it the same for others too), if I have such a PROCESS: PROC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I should add that

you will learn by (good) VHDL examples and tutorials on the web (Altera and others).

They represent many "basic" VHDL codes that you can understand very well.

port type in entities :

only std_logic(_vector) : Yes, conversions are annoying but more re-usable. I think about "design re-use".

I will study that question : I have wanted to keep a certain rigor in VHDL designing. Thanks for your opinion.