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port type in entities : only std_logic(_vector) : Yes, conversions are annoying but more re-usable. I think about "design re-use".
I will study that question : I have wanted to keep a certain rigor in VHDL designing. Thanks for your opinion.
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With Quartus (and other tools) supporting other things other than std_logic there is no reason to write what you mean. Doing all the type conversions just kills the whole point of types in VHDL, which are there for code readability. Adding in coversions all over the place makes the code more obscure.
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