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Honored Contributor
Honored ContributorVHDL - CASE related question
Hello, This is probably a very fundamental question but I'm a little confused as I am new to this. In VHDL (I'm sure it the same for others too), if I have such a PROCESS: PROC...
Altera_ForumHonored Contributor
Honored ContributorYou are right.
I began writing with other types (you had said) for port. And I finally adopt this method. This is less obscure, simpler to "debug".... Thanks
