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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL - CASE related question

Hello, This is probably a very fundamental question but I'm a little confused as I am new to this. In VHDL (I'm sure it the same for others too), if I have such a PROCESS: PROC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You are right.

I began writing with other types (you had said) for port. And I finally adopt this method.

This is less obscure, simpler to "debug"....

Thanks