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Thank you very mcuh Tricky, mmTsuchi.
Looks like a have long way to go.
One thing that I can't understand is,
A GENERATE block and a PROCESS block, 'how many' instructions can a FPGA perform? It ofcourse depends on the model, but as a programmer, how would you know that a block of code can be executed within a clock cycle? Or is it not like that? Is possible for a block of PROCESS to take several clock cycles to execute completely?
Thank you.
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an FPGA has no instructions, only logic gates and registers, so thats not a correct question to ask. You could write a CPU using VHDL and then you could ask your question about your CPU, not the FPGA.
A clocked Process will ALWAYS complete all code lines in a single clock cycle (assuming the FPGA can meet timing requirements), but thats may not be what you understand.
for example:
signal a, b : std_logic;
process(clk)
begin
if rising_edge(clk) then
a <= input
b <= a;
output <= b;
end if;
end process;
The code inside the process executes on every single clock cycle. The process discribed 3 registers connected. So it would take 3 clock cycles to get the input to the output. This is a 3 stage register pipeline.
The output would produce a new value every single clock cycle, delayed by 3 clocks.
I could put a generate block around this process like this:
multi_pipeline_gen : for i in 0 to 3 generate
--put process from before here
end generate multi_pipeline_gen;
and you get 4 parallel pipelines. Basically a process describes one bit of hardware, a generate tells you to replicated that hardware n times.
It sounds like you dont have a great understanding of digital electronics. Forget about VHDL for now and go and read up about digital logic.
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