Verilog/VHDL versus high level functions.

From what Ive seen, High level languages (I assume you mean OpenCL or C-to-gates) can produce decent results in the hands of a skilled designer - but the same can be said of VHDL and Verilog. All three can produce very good and very bad results. So I cant says they will all produce the same results.

The key is understanding the underlying architecture. If you dont understand the technology and try and write code as if you were a C programmer, you are doomed to fail in any language.

As for which to chose - Verilog is more like C (C programmers seem to hate VHDL because of the strict rules) but it has some pitfalls because of this.

And Quartus has the high level visual logic blocks and pll's, right.

Tho I think it's very cool to be able to use a lot of 1 bit signals and binary stuff.

Mostly for the core modules I would be confortable using 24bit floating point numbers. and A=A+1 style counting.

So it would be great to have that sort of thing in a readable format, but ofcourse there is nothing worse than finding out half way through things cant be done.

I was looking at VHDL for the demo apps, it seems a bit double in it's expressions but slowly grasping it. So you say Verilog is worth checking out for audio, or am I going to hit a major wall somewhere?

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And Quartus has the high level visual logic blocks and pll's, right.

Tho I think it's very cool to be able to use a lot of 1 bit signals and binary stuff.

Mostly for the core modules I would be confortable using 24bit floating point numbers. and A=A+1 style counting.

So it would be great to have that sort of thing in a readable format, but ofcourse there is nothing worse than finding out half way through things cant be done.

I was looking at VHDL for the demo apps, it seems a bit double in it's expressions but slowly grasping it. So you say Verilog is worth checking out for audio, or am I going to hit a major wall somewhere?

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HDL design can be classified into 3 levels (usually mixed by users):

structural: e.g. you instantiate a register directly wiring it, or instantiate an and function (ultimately mapped to luts)

logic (or not exactly data flow): e.g. you a <= b and C

behavioral: e.g. you describe in a sequential statement how a given node should behave.

In all cases the compiler settles and maps the code to luts and registers and other prefabricated blocks like rams, multipliers...etc.

It is certainly waste of time to go structural for things like registers which you can infer by behavioral description. You can also infer memories, multipliers (but not PLL) however I prefer structural approach to both rams and multipliers for good reasons as you may be given access to more features.

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I was looking at VHDL for the demo apps, it seems a bit double in it's expressions but slowly grasping it. So you say Verilog is worth checking out for audio, or am I going to hit a major wall somewhere?

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I may catch a lot of FLAK for this but I'd suggest you take a good look at VHDL first. It can do a few things Verilog can't like multi-dimensional arrays, nice functions and procedures.It has strict typing, which may look heavy in the beginning but you will get used to that after a while (and eventually end up liking that). There are a few VHDL editors that flag those syntax (and other) errors. E.g. Sigasi is a nice one, and for small projects it is free. There is also Emacs VHDL-mode.

Verilog is often said to be more C-like, IMHO it isn't, but the 'inventors' put this down as a sales argument against VHDL, which effectively has it roots in the Pascal / Modula / Ada languages. Now I remember that C in the 80's allowed a lot of assignments without warnings, wreaking havoc at some point or later. In that view Verilog may be C-like ;) My boss at the time used to say: "If you get a Pascal program compiled, it will run to some point. If you C-source compiles, you are nowhere yet."

There is also MyHDL, which is a Python based, it simulates fast and outputs either VHDL or Verilog for your Quartus project. Unfortunately it doesn't take advantage of VHDL's extra capabilities as it purposely supports both back-ends on an equal basis.

There is also Cx and PSHDL, but those are not quite complete yet.

A matter of preference. Verilog has enough sources online to get oneself to be proficient. VHDL would be a nightmare to start, due to the strict typing as mentioned by josyb.

By the way, functions and procedures are supported in Verilog-2001, and multi-dimensional arrays in system-Verilog (could be even earlier). Verilog as C-like would be an overstatement since if you write in C-style coding Verilog, high chances your code will not be synthesizable. Major difference is concurrency vs sequential, which most software programmers struggle with initially.

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A matter of preference. Verilog has enough sources online to get oneself to be proficient. VHDL would be a nightmare to start, due to the strict typing as mentioned by josyb.

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This sentence could also be stated the other way around: A matter of preference: VHDL has ample sources online to get oneself to be proficient. Verilog would be a nightmare to debug, due to the almost non-existent typing. :)

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I just want to restress - the arguments about the features of the languaes can be a real distraction - the important thing is understand the underlying basics - without understanding those, you cannot write any language well.

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Nice :D, The prospect of having all kinds of basic modules without losing speed over it seems great.

Think ill try some VHDL first. Probably means you havnt seen the last of me yet..