Verilog/VHDL versus high level functions.

From what Ive seen, High level languages (I assume you mean OpenCL or C-to-gates) can produce decent results in the hands of a skilled designer - but the same can be said of VHDL and Verilog. All three can produce very good and very bad results. So I cant says they will all produce the same results.

The key is understanding the underlying architecture. If you dont understand the technology and try and write code as if you were a C programmer, you are doomed to fail in any language.

As for which to chose - Verilog is more like C (C programmers seem to hate VHDL because of the strict rules) but it has some pitfalls because of this.