Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- A matter of preference. Verilog has enough sources online to get oneself to be proficient. VHDL would be a nightmare to start, due to the strict typing as mentioned by josyb. --- Quote End --- This sentence could also be stated the other way around: A matter of preference: VHDL has ample sources online to get oneself to be proficient. Verilog would be a nightmare to debug, due to the almost non-existent typing. :)