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Altera_Forum's avatar
Altera_Forum
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17 years ago

Verilog Package File

Hi All,

I have some lines of code in my project like,

Caseaddr[7:0]

8'b 00000000 : reg <= '1';

8'b 00000001 : reg <= '0';

-

-

8'b11111111 : reg <= '1'

Here i would like to replace address with some names like ,

Caseaddr[7:0]

Reg1 : reg <= '1';

Reg2 : reg <= '0';

-

-

Regn : reg <= '1'

I have made a file REG_PKG.v and defined like,

'define 8'b 00000000 Reg1

But still compiler is throwing error saying that, Reg1, reg2 etc is not declared.

Here, i have compiled the Package file and added line `include in my original code.

Please help me, how to make a constants file in verilog similar to vhdl.

regards,

freak

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Change:

    Case addr[7:0]

    Reg1 : reg <= '1';

    Reg2 : reg <= '0';

    -

    -

    Regn : reg <= '1'

    to

    Case addr[7:0]

    `Reg1 : reg <= 1;

    `Reg2 : reg <= 0;

    -

    -

    `Regn : reg <= 1;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    One of your problems is that your defines are backwards. Change your defines to be like:

    'define Reg1 8'b00000000

    Then use it like mguimod suggested

    Case addr[7:0]

    `Reg1 : reg <= 1;

    `Reg2 : reg <= 0;

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I would avoid using macros for this purpose. Macros (`define statements) are global to the entire project. I would use parameters instead. Specifically if you are using the Verilog 2001 or newer standard, I would make your REG_PKG.v file look like this: 

    localparam Reg1 = 8'b00000000;
localparam Reg2 = 8'b00000001;
localparam Reg3 = 8'b00000010;
...

    Then inside your module that actually implements the case statement use the "`include" statment like this: 

    `include "REG_PKG.v"
...
case (addr)
     Reg1 : reg <= '1';
     Reg2 : reg <= '0';
...
endcase
...

    Macros should be used with discretion.

    Jake