Verilog Package File

I would avoid using macros for this purpose. Macros (`define statements) are global to the entire project. I would use parameters instead. Specifically if you are using the Verilog 2001 or newer standard, I would make your REG_PKG.v file look like this:

localparam Reg1 = 8'b00000000;
localparam Reg2 = 8'b00000001;
localparam Reg3 = 8'b00000010;
...

`include "REG_PKG.v"
...
case (addr)
     Reg1 : reg <= '1';
     Reg2 : reg <= '0';
...
endcase
...