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Altera_Forum
Honored Contributor
Honored ContributorVerilog Package File
Hi All, I have some lines of code in my project like, Caseaddr[7:0] 8'b 00000000 : reg <= '1'; 8'b 00000001 : reg <= '0'; - - 8'b11111111 : reg <= '1' Here i would like to r...
Altera_ForumHonored Contributor
Honored ContributorI would avoid using macros for this purpose. Macros (`define statements) are global to the entire project. I would use parameters instead. Specifically if you are using the Verilog 2001 or newer standard, I would make your REG_PKG.v file look like this:
localparam Reg1 = 8'b00000000;
localparam Reg2 = 8'b00000001;
localparam Reg3 = 8'b00000010;
...`include "REG_PKG.v"
...
case (addr)
Reg1 : reg <= '1';
Reg2 : reg <= '0';
...
endcase
...
