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Altera_Forum's avatar
Altera_Forum
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17 years ago

Verilog Package File

Hi All, I have some lines of code in my project like, Caseaddr[7:0] 8'b 00000000 : reg <= '1'; 8'b 00000001 : reg <= '0'; - - 8'b11111111 : reg <= '1' Here i would like to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Change:

Case addr[7:0]

Reg1 : reg <= '1';

Reg2 : reg <= '0';

-

-

Regn : reg <= '1'

to

Case addr[7:0]

`Reg1 : reg <= 1;

`Reg2 : reg <= 0;

-

-

`Regn : reg <= 1;