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12 years ago

Verify fail at reset vektor after adding PLL

Hi.

Some days ago I've created a thread http://www.alteraforum.com/forum/showthread.php?t=42762

I think I asked questions wrong, however I can't delete it.

So, my system was running at 50MHz, everything was fine. I added it via Mega-Plugin-Wizzard: 


altpll_component : altpll
    GENERIC MAP (
        charge_pump_current_bits => 1,
        compensate_clock => "CLK0",
        inclk0_input_frequency => 20000,
        intended_device_family => "Cyclone IV E",
        loop_filter_c_bits => 0,
        loop_filter_r_bits => 27,
        lpm_hint => "CBX_MODULE_PREFIX=pll_sys",
        lpm_type => "altpll",
        m => 10,
        m_initial => 1,
        m_ph => 6,
        n => 1,
        operation_mode => "NORMAL",
        pll_type => "AUTO",
        port_activeclock => "PORT_UNUSED",
        port_areset => "PORT_UNUSED",
        port_clkbad0 => "PORT_UNUSED",
        port_clkbad1 => "PORT_UNUSED",
        port_clkloss => "PORT_UNUSED",
        port_clkswitch => "PORT_UNUSED",
        port_configupdate => "PORT_UNUSED",
        port_fbin => "PORT_UNUSED",
        port_inclk0 => "PORT_USED",
        port_inclk1 => "PORT_UNUSED",
        port_locked => "PORT_USED",
        port_pfdena => "PORT_UNUSED",
        port_phasecounterselect => "PORT_UNUSED",
        port_phasedone => "PORT_UNUSED",
        port_phasestep => "PORT_UNUSED",
        port_phaseupdown => "PORT_UNUSED",
        port_pllena => "PORT_UNUSED",
        port_scanaclr => "PORT_UNUSED",
        port_scanclk => "PORT_UNUSED",
        port_scanclkena => "PORT_UNUSED",
        port_scandata => "PORT_UNUSED",
        port_scandataout => "PORT_UNUSED",
        port_scandone => "PORT_UNUSED",
        port_scanread => "PORT_UNUSED",
        port_scanwrite => "PORT_UNUSED",
        port_clk0 => "PORT_USED",
        port_clk1 => "PORT_USED",
        port_clk2 => "PORT_UNUSED",
        port_clk3 => "PORT_UNUSED",
        port_clk4 => "PORT_UNUSED",
        port_clk5 => "PORT_UNUSED",
        port_clkena0 => "PORT_UNUSED",
        port_clkena1 => "PORT_UNUSED",
        port_clkena2 => "PORT_UNUSED",
        port_clkena3 => "PORT_UNUSED",
        port_clkena4 => "PORT_UNUSED",
        port_clkena5 => "PORT_UNUSED",
        port_extclk0 => "PORT_UNUSED",
        port_extclk1 => "PORT_UNUSED",
        port_extclk2 => "PORT_UNUSED",
        port_extclk3 => "PORT_UNUSED",
        self_reset_on_loss_lock => "ON",
        vco_post_scale => 2,
        width_clock => 5,
        c0_high => 3,
        c0_initial => 1,
        c0_low => 2,
        c0_mode => "odd",
        c0_ph => 6,
        c1_high => 3,
        c1_initial => 1,
        c1_low => 2,
        c1_mode => "odd",
        c1_ph => 0,
        clk0_counter => "c0",
        clk1_counter => "c1"
    )

After that I can't run code on my device. I get "Verify failed" at reset vektor or sometimes, if verification succed, no output appears, just the empty console window all the time.

My guess is, I've done something wrong with the PLL. I followed the steps from this here: http://www.emb4fun.de/fpga/nutos1/index.html and I only changed the speed grade to 7 according to my device datasheet EP4CE115F29C7. Phaseshift of c1 still be -54° for the SDRAM.

So what am I doing wrong? Is that maybe the lock range? I didn't found it in the pll.vhd and in Mega-Plugin-Wizzard you can't change it for CyclonIV E. I just realy don't know what to do anymore, maybe someone of you does.

Thank you.

Vlad

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