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Altera_Forum
Honored Contributor
Honored ContributorVerify fail at reset vektor after adding PLL
Hi. Some days ago I've created a thread http://www.alteraforum.com/forum/showthread.php?t=42762 I think I asked questions wrong, however I can't delete it. So, my system was running at...
Altera_ForumHonored Contributor
Honored ContributorI didn't go into the technical details for PLL tuning for SDRAM.I set the phase shift of -90 degree by trial and error method.
However you can take reference to calculate phase shift for SDRAM clock from the link given below. http://www.pldworld.com/_altera/html/_excalibur/nios-sdram-tuning/sdram_pll_tuning.pdf
