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Altera_Forum
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12 years ago

Verify fail at reset vektor after adding PLL

Hi. Some days ago I've created a thread http://www.alteraforum.com/forum/showthread.php?t=42762 I think I asked questions wrong, however I can't delete it. So, my system was running at...
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Altera_Forum
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12 years ago

I think it is the problem of SDRAM. You need to change the phase shift of the clock which is given to the SDRAM. You can use -90 degree clock to SDRAM clock.