Using Verilog Testbenches

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Hello everybody,

I am trying to simulate my desing using a verilog testbench, excerpts as follows at the end of my message.

Although I have checked that the testbench is included; logfiles show me that it has been included the post simulaiton results will not allow me to add any nodes to my resulting waveforms. Any ideas what I need to do ?

Thanks a bunch in advance for your answers -

Eric Hueckel

`timescale 1ns/1ns

module test_pwm_fail_detect;

reg clk_i;

reg pwm0_i;

reg pwm1_i;

reg pwm2_i;

reg pwm3_i;

reg global_enable_i;

wire pwm_fail_o;

// instantiate the pwm failure detector

pwm_fail_detect m1 (clk_i,

pwm0_i,

pwm1_i,

pwm2_i,

pwm3_i,

global_enable_i,

pwm_fail_o);

// $monitor($time, ,"clk_i=%b ,pwm0_i=%b,",

// clk_i,pwm0_i );

// initial# 1200 $stop;

initial

begin

clk_i = 1'b0; //set clock and reset low initially

global_enable_i = 1'b0;

pwm0_i = 1'b0;

pwm1_i = 1'b0;

pwm2_i = 1'b0;

pwm3_i = 1'b0;

end

always# 38 clk_i = ~clk_i; //toggle clk_i every 38 ns = 13.157 mhz

initial

begin

# 5 global_enable_i = 1'b1;

$stop; $finish;

end

endmodule

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Hi Eric,

how long is your testbench running ? With your posted testbench I would assume that the simulation will stop after 5ns ??? Which simualtion tool do you use ?

Kind regards

GPK

Hello GPK -

Thanks a bunch for your quick reply, I apprecaite it.

The Testbnech I showed was only to show how much testbench was

written, correct, only running 5 ns. I wasn't detailed enough in my

question which shold have stated, can I simulate a design using a verilog testbench in Quartus II ? I believe the answer is no, I can see the dialog

under

settings => simulator settings => simulation input

only calls for .vwf, .cvwf, .vec, .tbl, .scf, .vcd

and not .v files. It looks liek Quartus can't interpret a Verilog testbench,

is that right ?

Thanks again from southern Germany !!

Eric

--- Quote Start ---

Hello GPK -

Thanks a bunch for your quick reply, I apprecaite it.

The Testbnech I showed was only to show how much testbench was

written, correct, only running 5 ns. I wasn't detailed enough in my

question which shold have stated, can I simulate a design using a verilog testbench in Quartus II ? I believe the answer is no, I can see the dialog

under

settings => simulator settings => simulation input

only calls for .vwf, .cvwf, .vec, .tbl, .scf, .vcd

and not .v files. It looks liek Quartus can't interpret a Verilog testbench,

is that right ?

Thanks again from southern Germany !!

Eric

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Hi Eric,

as far as a know you can not use a verilog testbench with the Quartus build in simulator.

I use the simulator only for small simulations with only a few input vectors. For larger simulations I recommand to use simulator like Modelsim etc. A modelsim version is available on the Altera website, but I think it supports not multi languages designs.

Kind regards

GPK