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Altera_Forum's avatar
Altera_Forum
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17 years ago

Using Verilog Testbenches

Hello everybody, I am trying to simulate my desing using a verilog testbench, excerpts as follows at the end of my message. Although I have checked that the testbench is included; logfiles s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

--- Quote Start ---

Hello GPK -

Thanks a bunch for your quick reply, I apprecaite it.

The Testbnech I showed was only to show how much testbench was

written, correct, only running 5 ns. I wasn't detailed enough in my

question which shold have stated, can I simulate a design using a verilog testbench in Quartus II ? I believe the answer is no, I can see the dialog

under

settings => simulator settings => simulation input

only calls for .vwf, .cvwf, .vec, .tbl, .scf, .vcd

and not .v files. It looks liek Quartus can't interpret a Verilog testbench,

is that right ?

Thanks again from southern Germany !!

Eric

--- Quote End ---

Hi Eric,

as far as a know you can not use a verilog testbench with the Quartus build in simulator.

I use the simulator only for small simulations with only a few input vectors. For larger simulations I recommand to use simulator like Modelsim etc. A modelsim version is available on the Altera website, but I think it supports not multi languages designs.

Kind regards

GPK