Using Verilog Testbenches

Hello GPK -

Thanks a bunch for your quick reply, I apprecaite it.

The Testbnech I showed was only to show how much testbench was

written, correct, only running 5 ns. I wasn't detailed enough in my

question which shold have stated, can I simulate a design using a verilog testbench in Quartus II ? I believe the answer is no, I can see the dialog

under

settings => simulator settings => simulation input

only calls for .vwf, .cvwf, .vec, .tbl, .scf, .vcd

and not .v files. It looks liek Quartus can't interpret a Verilog testbench,

is that right ?

Thanks again from southern Germany !!

Eric