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Altera_Forum's avatar
Altera_Forum
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15 years ago

using memory Bits

Hi i wrote a vhdl design in which i wanted to buffer data like this:

WHEN 0 => ausgangimag0 <=ausgangimag0 + resultim;ausgang2 <= ausgangimag0;

WHEN 1 => ausgangimag1 <=ausgangimag1 + resultim;ausgang2 <= ausgangimag1;

WHEN 2 => ausgangimag2 <=ausgangimag2 + resultim;ausgang2 <= ausgangimag2;

WHEN 3 => ausgangimag3 <=ausgangimag3 + resultim;ausgang2 <= ausgangimag3;

WHEN 4 => ausgangimag4 <=ausgangimag4 + resultim;ausgang2 <= ausgangimag4; .... and so on

only much more. when i compile the design i get the error: "Error: Design contains 77634 blocks of type combinational node. However, device contains only 33216." But the memory Bits of the FPGA are empty (0 / 483840). How can i use them to buffer the data?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Generally you have to observe the rules for RAM inference. Using the same signal for RAM read and write as in ausgangimag1 <=ausgangimag1 + resultim doesn't work I think. You should show the complete process layout for clarification.

    You better start from the Quartus VHDL templates.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    do you want to store it in regsiters or in RAM-cells ?

    obviously you dindt make any storage elements, so all of your assignments

    lead to a pure combinational logic