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Altera_Forum's avatar
Altera_Forum
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16 years ago

using memory Bits

Hi i wrote a vhdl design in which i wanted to buffer data like this: WHEN 0 => ausgangimag0 <=ausgangimag0 + resultim;ausgang2 <= ausgangimag0; WHEN 1 => ausgangimag1 <=ausgangimag1 + resultim;...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Generally you have to observe the rules for RAM inference. Using the same signal for RAM read and write as in ausgangimag1 <=ausgangimag1 + resultim doesn't work I think. You should show the complete process layout for clarification.

You better start from the Quartus VHDL templates.