Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorusing memory Bits
Hi i wrote a vhdl design in which i wanted to buffer data like this: WHEN 0 => ausgangimag0 <=ausgangimag0 + resultim;ausgang2 <= ausgangimag0; WHEN 1 => ausgangimag1 <=ausgangimag1 + resultim;...
Altera_ForumHonored Contributor
Honored ContributorRead this document (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf) to learn how to properly infer memories in VHDL code.
