G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This serial data (data rate for each serial stream is 700Mbps maximum) is read with Cyclon III. What´s the best way to do this ? I found the ALTLVDS Megafunction, but i think this block has no sense, cause of the serialization factor of 1 for each channel used in my system. But what´s the best way to read and process the sampled input data ?? Is it possible to wire this LVDS Serial data direct to a PIO ??? hope someone can help me greets !!!

What ADC, I mean can you give us the Partnumber?

hey.. it´s analogs ad9252 thanks

The serialisation factor in your system is actually 14. The ALTLVDS does not support this, but you could set it to handle a deserialisation of 7 bits and concatenate two 7-bit packets into one 14 bit. ALTLVDS however uses a PLL to sample the inputs, so if you have multiple devices, ADCs in this case) you may run out of PLLs. However as the outputs of the ADC are nicely source synchronous and are accompanied by a dataclock and a frame-indicator , you can easily deserialise the ADC data channels with simple shiftregisters. Feed the inputs into a DDR-In block and then serialise the 2 bits in a 7-bit shiftregister each. assemble the 2 7-bit buses into a 14-bit bus and define the right moment to register it. You need to do some work to constrain all this though. I have done this for ADS527x and AD9222 octal ADCs, unfortunately my code is in AHDL (I do use VHDL nowadays).

Hi there !!! Are u sure about the value of the serialisation factor? I thought that a serialisationfactor unequal one is only possible if i would mix, say 2 channels, together and transfer the data alternating. so for mixing 2 channels gives an serialisationfactor or deserialisationfactor of 2, so every second bit (beginning with bit 0) belongs to channel 1 and all other to channel 2. So it doesn´t matter how many bits belong to one datastream or sampled value. I´m not sure about but i thought that i found this out while reading through altlvds documentation. The problem with running out of PLL came also to my mind as i will use more devices so i think i´ll have to find ways to work without the megafunction and use the dataclock and frame-indicator in combination with shiftregisters... So the solution u provided in your previous post is this possible solution using altlvds or not ? what´s this ddr-in block ? Is it possible to go in shiftregisters with differential signals ?? thanks for helping greets

AD9252 is basically similar to AD9222, expect for a resolution of 14 versus 12 bit. I completely agree with josyb about the suggested solution (DDIO + shift register). Also the deserialization factor of 14 is correct. Strictly spoken, you won't necessarily need a PLL for the receiver, because the ADC provide both fast and slow (respectively bit and frame) clock. but, 700 Mbps is pretty on the edge, a means to adjust the clock phases manually may turn out to be badly required. A receiver PLL would use the frame clock (FCO) as input clock and generate the fast clock. You can also connect both ADC clocks to the FPGA and keep all options. See below a VHDL example of 4-channel 14-Bit ADC receiver, that can be easily changed to 8 Channels. chan: FOR I IN 0 TO 3 GENERATE lvds_rcv : altddio_in GENERIC MAP ( intended_device_family => "Cyclone III", invert_input_clocks => "ON", lpm_type => "altddio_in", power_up_high => "OFF", width => 1 ) PORT MAP ( datain => AD9259_D(I DOWNTO I), inclock => fastclock, dataout_h => dataout_h(I DOWNTO I), dataout_l => dataout_l(I DOWNTO I) ); PROCESS (fastclock) BEGIN IF rising_edge(fastclock) THEN lvds_sr(I) <= lvds_sr(I)(11 downto 0) & dataout_l(I) & dataout_h(I); END IF; END PROCESS; PROCESS (slowclock) BEGIN IF reset = '1' THEN lvds_rx(I) <= (others => '0'); ELSIF rising_edge(slowclock) THEN lvds_rx(I) <= lvds_sr(I); END IF; END PROCESS; END GENERATE;

using lvds | Altera Community

45 Replies

Altera_Forum
Honored Contributor
12 years ago
TO_BE_DONE
Altera_Forum
Honored Contributor
9 years ago
Hi josyb,

Is it means that 350MHz would get 700Mbps data rate? Cause of DDR.
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
Hi josyb,

Is it means that 350MHz would get 700Mbps data rate? Cause of DDR.
--- Quote End ---

Yes, it will.
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
Yes, it will.
--- Quote End ---

Hi josyb,

Thanks for you reply!

I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output. I don't know the maximum speed of these column I/O LVDS pairs, and the datasheet only give the row I/O LVDS pairs speed range. Do you think the column I/O lvds pairs can run at 700Mbps or more than this speed?
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
I'm going to using Stratix IVGX deivce, and have to use column I/O LVDS pairs to receive ADC output. I don't know the maximum speed of these column I/O LVDS pairs, and the datasheet only give the row I/O LVDS pairs speed range. Do you think the column I/O lvds pairs can run at 700Mbps or more than this speed?
--- Quote End ---

The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ...
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
The Device Datasheet doesn't mention any difference between Row and Column IO, so I'm pretty sure that 700 Mbps will be fine. But you can easily try that out ...
--- Quote End ---

Hi josyb,

ADC's output speed is up to 1.6Gbps, even run at 2-lane mode, the LVDS pairs speed at FPGA side will be 800Mbps. If LVDS pairs connect to column I/O LVDS pairs, means shift register will run at 800MHz. Does core logic run at so high speed?
Altera_Forum
Honored Contributor
9 years ago
Jerry,

800Mbps will result in a 400 MHz clock,which is delivered by the ADC, usually 90 degree shifted (center-aligned). But this clock will only be used to shift the first 4 (5, 6, 7 or 8 ) stages resulting into two 4 (5,6,7 or 8) vectors that will then be combined to the final 8 (10,12,14 or 16) bit word. The ADC usually has a frameclock signal that you can derive a signal from to transfer the received word back into the base clock of 100 MHz which can be handled 'hands down' by the FPGA fabric
The LTM9010 in 14-bit 2-Lane mode is only slightly more complicated in that it sends out a half-rate FR-clock, delivering two 14-bit samples every other base clock, but you can multiplex that back up to one 14-bit sample per clock.

Regards,
Josy
Altera_Forum
Honored Contributor
9 years ago
Hi josyb,

Thanks for you reply.

--- Quote Start ---
delivering two 14-bit samples every other base clock,
--- Quote End ---

Is here should be 7-bit?

Do you have some thought about the synchronization among channels and devices?

Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA?
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---

Is here should be 7-bit?

Do you have some thought about the synchronization among channels and devices?

Can i use internal system clock as the shift-regiters clock? And the ADCs' DCO signals can't be routed to FPGA?
--- Quote End ---

The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks)
You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure.

Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements.

Regards,

Josy
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
The picture on page 8 in the data-sheet of the LTM9010 shows 2 ADC words are transmitted per FR-cycle (using 7 DCO clocks)
You can use an internal clock for the DDR-IN and the following shift-registers, but then you will have to align the incoming LVDS data using extra logic. It would save you from routing the 6 * 2 (*2) wires for the DCO and the FR signals. If you have enough clock inputs available on your Stratix device, I would recommend using DCO and FR; it gives you a nice static timing closure.

Synchronisation between devices: the only concern is that the encoding clock is synchronous for all ADC-chips: keeping them equal in length is one thing. The other is perhaps drive them from a clock distribution IC giving you very tight timing, it depends on your requirements.

Regards,

Josy
--- Quote End ---

Hello Josy,

Thanks for you help.

I'm testing LVDS module in Quartus II, can you tell me about implementing bitslip method?

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