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Altera_Forum
Honored Contributor
Honored Contributorusing lvds
G´day !!
I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This serial data (data rate for each serial stream is 700Mbps maximum) is read with Cyclon III. What´s the best way to do this ? I found the ALTLVDS Megafunction, but i think this block has no sense, cause of the serialization factor of 1 for each channel used in my system. But what´s the best way to read and process the sampled input data ?? Is it possible to wire this LVDS Serial data direct to a PIO ??? hope someone can help me greets !!!45 Replies
Altera_ForumTO_BE_DONE
- Altera_Forum
i just thought in giving out the result vektor (parallelized sampled data) on an output port...
- Altera_Forum--- Quote Start --- how do u write to an out port as effectively as possible ? --- Quote End --- Effectively in what regard? And which outport?
- Altera_Forum
ok, i´m glad i´ve the same, but how do u write to an out port as effectively as possible ?
- Altera_Forum
TYPE RXTYPE IS ARRAY (0 to 3) of STD_LOGIC_VECTOR(13 downto 0); SIGNAL lvds_rx : RXTYPE; SIGNAL lvds_sr : RXTYPE; - Altera_Forum
thank u for helping..
@FvM, i´ve tried to implement your type of solution. but how do i´ve to declare lvds_sr and lvds_rx so that there is no error in synthesis.... phh it´s long time ago i´ve done vhdl coding, so sorry for that "stupid" question... - Altera_Forum
I didn't have 4 PLLs in the EP2C8 so I had to do without.
I recompiled my block for 350 MHz and adjusted the .sdc for the changed timings and relations. The Multicorner Datasheet reports 150 ps Setup time and 344 ps Hold time for the Data inputs, which is well within the 414 ps as calculated from the ADC's datasheet. The 'auto' device selected by the compiler is an EP2C5T144C6. On my 'real' design with 4 octals, and 300 MHz operation, the worst case setup is 277 ps and the worst case hold is 422 ps. Two of the blocks have standard Clk inputs, the two other have DPClk inputs. I'm not a fan of the 'training' approach (sometimes it can't be avoided though), it just bloats the resource usage, complicates start-up, and it this case is not necessary. - Altera_Forum--- Quote Start --- There maybe a couple of pitfalls in using both the fastclock and the slowclock. --- Quote End --- I didn't explicitely mention, that fast- and slowclock in my VHDL code are both PLL output clocks, adjusted for maximum skew margin and correct data receiption. If the receiver is intended for operation without PLL, an addional synchronous FCO delay would be required. My favourite solution for bitrates near the Cyclone III limits is a receiver PLL with automatic bit phase adjustment, utilizing the ADC test mode and Cyclone III PLL dynamic phase shift. --- Quote Start --- 2.) i can type in the deserialization factor of 14 manually, and in handbook it´s mentioned "if the number is not available to choose, type the desired number in this box"! do u think that this won´t function? 3.) if it is possible to tpye in 14 isn´t it better to use lvds megafunction instead of ddio and shiftregister --- Quote End --- As far as I remember, the MegaFunction allows it, but the RTL and gate level synthesis result looks rather strange. If the processing hasn't changed since Quartus 8, DDIO + shift register will be better, I think. At least it's working correctly. --- Quote Start --- 4.) i if i use DDIO (it´s double data rate megafunction i reckon) and shiftregister (i suppose that this solution works without altlvds megafunction) i´m wondering if this also works with lvds input signals ??? --- Quote End --- You should have noticed, that both josyb's and my references are dealing with LVDS interfaces. Actually, LVDS is just an I/O standard, that can be assigned to an input port (if it's connected to the non-inverted pin of a differential pin pair).
- Altera_Forum
thanks guys for helping !
but now i´m a little bit confused about all that :-) 1.) serialization/deserialization, ok i misunderstood all that stuff 2.) i can type in the deserialization factor of 14 manually, and in handbook it´s mentioned "if the number is not available to choose, type the desired number in this box"! do u think that this won´t function? 3.) if it is possible to tpye in 14 isn´t it better to use lvds megafunction instead of ddio and shiftregister 4.) i if i use DDIO (it´s double data rate megafunction i reckon) and shiftregister (i suppose that this solution works without altlvds megafunction) i´m wondering if this also works with lvds input signals ??? greets - Altera_Forum
There maybe a couple of pitfalls in using both the fastclock and the slowclock:
1. the last falling edge (clocking in the LSB ) is only 1/4 Tc before the slowclock rising which comes down to 714 ps only. 2. at slowclock rising the last two bits are not yet in the shiftregister It is IMHO advisable to use the slowclock as a data input (if you look at the timing diagram you can see that it has the same timing as the data outputs) and derive a transfer signal from it to clock the shifregister info into the output register. I managed 4 octals (ADS527x) at 300 MHz in a EP2C8F256C6. The datasheet report shows some headroom for the setup and hold ties, so I think the 350MHz should be quite feasible too. Using a single clock to do all the work will help too.
