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There maybe a couple of pitfalls in using both the fastclock and the slowclock.
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I didn't explicitely mention, that fast- and slowclock in my VHDL code are both PLL output clocks, adjusted for maximum skew margin and correct data receiption. If the receiver is intended for operation without PLL, an addional synchronous FCO delay would be required.
My favourite solution for bitrates near the Cyclone III limits is a receiver PLL with automatic bit phase adjustment, utilizing the ADC test mode and Cyclone III PLL dynamic phase shift.
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2.) i can type in the deserialization factor of 14 manually, and in handbook
it´s mentioned "if the number is not available to choose, type the desired
number in this box"! do u think that this won´t function?
3.) if it is possible to tpye in 14 isn´t it better to use lvds megafunction instead of ddio and shiftregister
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As far as I remember, the MegaFunction allows it, but the RTL and gate level synthesis result looks rather strange. If the processing hasn't changed since Quartus 8, DDIO + shift register will be better, I think. At least it's working correctly.
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4.) i if i use DDIO (it´s double data rate megafunction i reckon) and shiftregister (i suppose that this solution works without altlvds megafunction) i´m wondering if this also works with lvds input signals ???
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You should have noticed, that both josyb's and my references are dealing with LVDS interfaces. Actually, LVDS is just an I/O standard, that can be assigned to an input port (if it's connected to the non-inverted pin of a differential pin pair).
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