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Honored Contributor
Honored Contributorusing lvds
G´day !! I´m using an ADC with differential output (LVDS). It´s a device including 8 ADCs with Serial LVDS output. Data from each ADC is serialized and provided on a seperate channel. This seri...
Altera_ForumHonored Contributor
Honored ContributorThere maybe a couple of pitfalls in using both the fastclock and the slowclock:
1. the last falling edge (clocking in the LSB ) is only 1/4 Tc before the slowclock rising which comes down to 714 ps only. 2. at slowclock rising the last two bits are not yet in the shiftregister It is IMHO advisable to use the slowclock as a data input (if you look at the timing diagram you can see that it has the same timing as the data outputs) and derive a transfer signal from it to clock the shifregister info into the output register. I managed 4 octals (ADS527x) at 300 MHz in a EP2C8F256C6. The datasheet report shows some headroom for the setup and hold ties, so I think the 350MHz should be quite feasible too. Using a single clock to do all the work will help too.
