I didn't have 4 PLLs in the EP2C8 so I had to do without.
I recompiled my block for 350 MHz and adjusted the .sdc for the changed timings and relations. The Multicorner Datasheet reports 150 ps Setup time and 344 ps Hold time for the Data inputs, which is well within the 414 ps as calculated from the ADC's datasheet. The 'auto' device selected by the compiler is an EP2C5T144C6.
On my 'real' design with 4 octals, and 300 MHz operation, the worst case setup is 277 ps and the worst case hold is 422 ps. Two of the blocks have standard Clk inputs, the two other have DPClk inputs.
I'm not a fan of the 'training' approach (sometimes it can't be avoided though), it just bloats the resource usage, complicates start-up, and it this case is not necessary.