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Altera_Forum
Honored Contributor
Honored ContributorUse defines in Verilog
I have some problems using defines in Verilog.
I want to define memory depth & width, and then to use these defines for the memory name. For example - memory name should be ram512x32 `define depth 512 `define width 32 `define memory_name ram `depth x `width Is there a way to do it in Verilog ?3 Replies
Altera_ForumYou need System Verilog, I don't think you can do that on Verilog-2001. I don't know if this System Verilog feature is supported by Quartus, but you could try.
- Altera_Forum
The problem in this case is assembling a continuous text string. Preprocessor define directive requires white spaces separating the arguments, that isn't suitable in this case. There may be an option to achieve your intention through "$" system functions, but I'm not used to it.
- Altera_Forum
You can use parameter.
For example: parameter depth = 512; etc.
