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Altera_Forum's avatar
Altera_Forum
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17 years ago

Use defines in Verilog

I have some problems using defines in Verilog. I want to define memory depth & width, and then to use these defines for the memory name. For example - memory name should be ram512x32 `def...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The problem in this case is assembling a continuous text string. Preprocessor define directive requires white spaces separating the arguments, that isn't suitable in this case. There may be an option to achieve your intention through "$" system functions, but I'm not used to it.