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Altera_Forum
Honored Contributor
Honored ContributorUse defines in Verilog
I have some problems using defines in Verilog. I want to define memory depth & width, and then to use these defines for the memory name. For example - memory name should be ram512x32 `def...
Altera_ForumHonored Contributor
Honored ContributorYou need System Verilog, I don't think you can do that on Verilog-2001. I don't know if this System Verilog feature is supported by Quartus, but you could try.
