Use a FPGA to flash the Nios II program in another FPGA

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I have the following problem: I have to work with a system in which I have a first FPGA which controls the JTAG port of a second FPGA. In this second FPGA I have a Nios II softcore running, which requires a software update. That software update is in the form of a .flash file.

I cannot access to the first FPGA with a JTAG from the computer... so, in order to performing the operation, I have to emulate that JTAG master procedure in my first FPGA.

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What communication do you have to the first FPGA?

What does the .flash file get programmed to; an external EPCS EEPROM or parallel Flash?

Do you have any other connection between the two FPGAs?

Assuming the only way you can communicate via FPGAs is using the JTAG interface, you can create an Avalon-to-JTAG bridge in the first FPGA, and a JTAG-to-Avalon bridge in the second FPGA. The first FPGA can then just read/write to the memory map of the second FPGA.

At that point, its pretty simple to copy data to the memory map of the second FPGA, so that you can pass it to a flash programmer.

Please provide more details on how you connect the first FPGA to a computer, and then how the two FPGAs are connected.

Cheers,

Dave

The first FPGA communicates with a remote processor (microcontroller) being integrated in its memmory space. The microcontroller has a serial connection with a PC.

It is a parallel flash what has to be programmed... but the second FPGA is a blackbox for me (I have no documentation at all... and no posibility of programming anything in it other than blindly...). The only communication between the FPGAs is the JTAG connection and some information buses for the operation the second FPGA does.

The problem is that, in my opinion, I can only perform the update operation by generating the same stream as the computer would do directly with the JTAG... for this I would need some kind of help interpreting what is in the .flash file (has it got headers or any information I should not directly copy through the JTAG?) and also about the protocol the altera programmer uses... I have searched quite a lot in the documentation but I was not able to find anything useful.

Thank you very much for your help :)

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The first FPGA communicates with a remote processor (microcontroller) being integrated in its memmory space. The microcontroller has a serial connection with a PC.

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Sorry, can you be a little clearer. The hierarchy of machines is:

1) Control PC, with a serial connection to the first FPGA.

2) First FPGA - with a microcontroller in its memory map, and a serial connection to the PC

3) Second FPGA - black box, with parallel flash connected to it.

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It is a parallel flash what has to be programmed... but the second FPGA is a blackbox for me (I have no documentation at all... and no posibility of programming anything in it other than blindly...). The only communication between the FPGAs is the JTAG connection and some information buses for the operation the second FPGA does.

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If its a black box, how do you know what the JTAG protocol is and that you can program the flash? Perhaps you mean its a design that you cannot change, but you do know that it contains a JTAG-to-Avalon-MM bridge, and you do know the memory map.

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The problem is that, in my opinion, I can only perform the update operation by generating the same stream as the computer would do directly with the JTAG...

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So how are you doing that now? Via JTAG connected to both the first and second FPGAs, or just to the second FPGA?

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for this I would need some kind of help interpreting what is in the .flash file (has it got headers or any information I should not directly copy through the JTAG?)

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What is producing the .flash image? What is it for? Read it with an editor in binary mode.

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and also about the protocol the altera programmer uses...

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There are several protocols that is could be using; it depends on what the logic is in your black box. You can read the HUB_INFO and the NODE_INFO from the JTAG interface to determine what components exist in the design. See the SLD Virtual JTAG guide, and

http://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/vjtag.pdf)

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I have searched quite a lot in the documentation but I was not able to find anything useful.

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There is some information in the Altera docs, other information on the web, and ultimately information you need to gather with a logic analyzer.

Cheers,

Dave

Hallo again,

the jerarchy would be:

control pc --- serial ---> microcontroller ---memory space---> 1st fpga ---JTAG--->2nd fpga

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So how are you doing that now? Via JTAG connected to both the first and second FPGAs, or just to the second FPGA?

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Now I can access to the JTAG pins, but I will not in the future, as the whole system will have to be enclosed. I can now directly update the second FPGA, but it is just while debugging.

The .flash file looks like this (the beginnin), with the notepad:

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S0200000496E647573747269616C45746865726E65744D6F64756C2E666C61736844

S32500000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA

S3250000002056EFEFEFEFCFCFCFDFDF9FDFDF8F9F9FBFBF9FBFFFDFBF9FFFDFFFFF9F9F9F9FE3

S32500000040BF9FBFBF9FBF9FDFDF16E8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A

S32500000060FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9A

S32500000080FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A

S325000000A0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5A

S325000000C0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A

S325000000E0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1A

S32500000100FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9

S32500000120FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD9

S32500000140FFFFFFFFFFFFFFFFFFFF000000000101010100000000010101010000000000009B

S32500000160000000000000000000000000000000000000000000000000000000000000000079

S32500000180000000000000000000000000000000000000000000000000000000000000000059

S325000001A0000000000000000000000000000000000000000000000000000000000000000039

S325000001C0000000000000000000000000000000000000000000000000000000000000000019

S325000001E00000000000000000000000000000000000000000000000000000000000000000F9

S325000002000000000000000000000000000000000000000000000000000000000000000000D8

S325000002200000000000000000000000000000000000000000000000000000000000000000B8

S32500000240000000000000000000000000000000000000000000000000000000000000000098

S325000002600000000000000000000000000000000000000000000000000000202020200000F8

S32500000280000000000000000000000000000000000000000000000000000000000000000058

S325000002A00000000000000000000000000000000000000000000000000000202020200000B8

S325000002C0000020202020000000000000000020202020000000000000000000000000000018

S325000002E0000020202020202020202020202000000000000000001010101000000000101018

S325000003001010000000000000000000000000000000000000000000000000000000000000B7

S32500000320000020202020202020200000000000000000020202022222222220202020202067

S32500000340202020202020222222222222222222222222222222222222222222222222222263

S325000003602222222222222222222222222222222222222222222222222222020202020202F7

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I guess I would receive not good values if I opened it with a binary editor... as it seems that all lines have some kind of coding for the programmer and then data in Hex format... my doubt here, is which of this information do I have to send and how...

Thank you very much!

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the hierarchy would be:

control pc --- serial ---> microcontroller ---memory space---> 1st fpga ---JTAG--->2nd fpga

Now I can access to the JTAG pins, but I will not in the future, as the whole system will have to be enclosed. I can now directly update the second FPGA, but it is just while debugging.

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That sounds like a very poor design ...

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The .flash file looks like this (the beginnin), with the notepad:

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Its a Motorola S-record format file:

http://en.wikipedia.org/wiki/srec_%28file_format%29

You need to write (or find) some code to turn this back into (address,data) pairs, so that you can then program your flash. Actually, look at the bottom of the Wikipedia entry; gnu binutils (http://en.wikipedia.org/wiki/gnu_binutils) objdump and objcopy programs can produce and display S-records.

However, you have yet to confirm that you know the protocols required to perform the flash programming via JTAG. If the only way to get the the second FPGA is to use its JTAG now while the box is open for debugging, just use the JTAG programmer you have now. You're wasting your time trying to figure out details that you cannot use in the final system.

Cheers,

Dave

Thank you very much for your information.

I do not know very well what do you mean by knowing the protocols required to perform the flash programming. I know general JTAG protocol to perform boundary scan, but I do not know if I can access to any specific documentation for the Altera flash programming.

If you can refer some documentation it would be really helpful.

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I do not know very well what do you mean by knowing the protocols required to perform the flash programming. I know general JTAG protocol to perform boundary scan, but I do not know if I can access to any specific documentation for the Altera flash programming.

If you can refer some documentation it would be really helpful.

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The relevant Altera documentation depends on what you are calling 'flash'.

Is it a parallel NOR flash device, a parallel NAND flash device, or perhaps a serial version? Is it connected to GPIOs on the FPGA, or is it a standard Altera flash device wired to the programming pins on the FPGA?

Did you want to program the flash using a custom configuration in the second FPGA, or did you want to use an Avalon-MM interface in the existing design, or did you want to use the JTAG boundary cells?

As you see, there are lots of details you have neglected to mention.

If you can provide details on your design, eg., a link to the board schematics, or can ask a detailed question, then users on this forum can help.

Cheers,

Dave