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I do not know very well what do you mean by knowing the protocols required to perform the flash programming. I know general JTAG protocol to perform boundary scan, but I do not know if I can access to any specific documentation for the Altera flash programming.
If you can refer some documentation it would be really helpful.
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The relevant Altera documentation depends on what you are calling 'flash'.
Is it a parallel NOR flash device, a parallel NAND flash device, or perhaps a serial version? Is it connected to GPIOs on the FPGA, or is it a standard Altera flash device wired to the programming pins on the FPGA?
Did you want to program the flash using a custom configuration in the second FPGA, or did you want to use an Avalon-MM interface in the existing design, or did you want to use the JTAG boundary cells?
As you see, there are lots of details you have neglected to mention.
If you can provide details on your design, eg., a link to the board schematics, or can ask a detailed question, then users on this forum can help.
Cheers,
Dave
Honored Contributor
