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I have the following problem: I have to work with a system in which I have a first FPGA which controls the JTAG port of a second FPGA. In this second FPGA I have a Nios II softcore running, which requires a software update. That software update is in the form of a .flash file.
I cannot access to the first FPGA with a JTAG from the computer... so, in order to performing the operation, I have to emulate that JTAG master procedure in my first FPGA.
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What communication do you have to the first FPGA?
What does the .flash file get programmed to; an external EPCS EEPROM or parallel Flash?
Do you have any other connection between the two FPGAs?
Assuming the only way you can communicate via FPGAs is using the JTAG interface, you can create an Avalon-to-JTAG bridge in the first FPGA, and a JTAG-to-Avalon bridge in the second FPGA. The first FPGA can then just read/write to the memory map of the second FPGA.
At that point, its pretty simple to copy data to the memory map of the second FPGA, so that you can pass it to a flash programmer.
Please provide more details on how you connect the first FPGA to a computer, and then how the two FPGAs are connected.
Cheers,
Dave
Honored Contributor
