USB Blaster VCC

I use a very similar design, with 74LVCs powered at 3.3V (because this is the Vccio of my bank# 1), and 33 Ohm resistors in series. I have other components in the JTAG chain, and the possibility to move resistors to exclude them from the chain and have only the FPGA (yes, I don't trust the Quartus programmer that much :D ).

You must be sure that the buffers you use are fast enough for the Jtag signals.

Dave and Daixiwen; Thank you for your comments. Dave, the schematic that you provided a link to is most interesting . . . so the 100 ohm buffer's in Dave's schematic provide the resistive damping in the equivalent RLC circuit that would exist on the PCB between the JTAG pins and the FPGA itself . . . buffered of course. I like it. This limits the energy going into the FPGA pins that are JTAG, which are basically designated as 2.5V for truly safe operation . .

I have thought for a long time to make a small board that would be a JTAG adapter. It would have a CPLD on it, that would take in multiple types of JTAG cables (Altera and Terasic/Altera clones, for example) and then provide the appropriate target board JTAG signals, whether the target board be at 100 mil pitch, 50 mil pitch, etc. What you have done is very similar to this, but located on the board itself, and with digital logic rather than a CPLD.

Thanks! James

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Dave, the schematic that you provided a link to is most interesting . . . so the 100 ohm buffer's in Dave's schematic provide the resistive damping in the equivalent RLC circuit that would exist on the PCB between the JTAG pins and the FPGA itself . . . buffered of course. I like it. This limits the energy going into the FPGA pins that are JTAG, which are basically designated as 2.5V for truly safe operation . .

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The resistor can be used for several purposes;

1) The traces are nominally source terminated transmission lines. The ideal resistance for a source termination is that it plus the driver output impedance match the transmission line impedance (typically 50-Ohms or 65-ohms depending on the trace and PCB geometry).

2) You can use it to slow down the rise-time of the buffer output; the R acts with the C load (the trace and the capacitance of the end pad).

3) Its a debug feature; you can start lifting resistors to remove components from the JTAG chain. I've had cases where an FPGA is dead. I can jumper over it, check everything else is working, and then get the FPGA removed. The placement of the board was reviewed with the assembly company (SigmaTron) to ensure the board could be reworked.

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I have thought for a long time to make a small board that would be a JTAG adapter. It would have a CPLD on it, that would take in multiple types of JTAG cables (Altera and Terasic/Altera clones, for example) and then provide the appropriate target board JTAG signals, whether the target board be at 100 mil pitch, 50 mil pitch, etc. What you have done is very similar to this, but located on the board itself, and with digital logic rather than a CPLD.

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The problem with this type of board is that there is no generic hook into the Altera software. To make a general purpose board, you need to have your adapter be able to fool Quartus into thinking it is communicating with a USB Blaster. That information is not provided by Altera, however, there is enough information on the internet to build your own FT245+CPLD or Cypress FX2 USB-Blaster. Its an interesting challenge :)

Cheers,

Dave

Coming back to a previous question:

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I am curious if anyone has consistently designed the JTAG header at VCC of 3.3V and had the FPGA successfully program time after time? With or without clamping diodes?

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The 2.5V JTAG supply suggestion has been newly introduced by Altera with Cyclone III, together with a bunch of "Watch your step" statements related to the danger of input overvoltage. Curiously, the overvoltage specification is nearly unchanged between Cyclone II and Cyclone III. The real device overvoltage capability has changed of course with the technology and in so far it's quite reaonable to look more thoroughly on some problems that existed since long.

Overshoot of JTAG signals is mainly a matter of reasonable termination respectively transmission line impedance design, so you can achieve non-overshoot JTAG signals. As already discussed, clamp diodes are also an effective way. But a vendor suggestion need to consider different programming hardware, modified JTAG cables and different board routing. So I understand, why Altera promotes 2.5 V JTAG. It's your decision to follow or ignore the suggestion.

Most JTAG circuits designed by my customers or myself are still using 3.3V. Only part of it (mostly industrial boards) is utilizing clamp diodes.