USB Blaster VCC

Dave and Daixiwen; Thank you for your comments. Dave, the schematic that you provided a link to is most interesting . . . so the 100 ohm buffer's in Dave's schematic provide the resistive damping in the equivalent RLC circuit that would exist on the PCB between the JTAG pins and the FPGA itself . . . buffered of course. I like it. This limits the energy going into the FPGA pins that are JTAG, which are basically designated as 2.5V for truly safe operation . .

I have thought for a long time to make a small board that would be a JTAG adapter. It would have a CPLD on it, that would take in multiple types of JTAG cables (Altera and Terasic/Altera clones, for example) and then provide the appropriate target board JTAG signals, whether the target board be at 100 mil pitch, 50 mil pitch, etc. What you have done is very similar to this, but located on the board itself, and with digital logic rather than a CPLD.

Thanks! James