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Altera_Forum's avatar
Altera_Forum
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10 years ago

Transceiver PCS Question

When implementing GIGE on CycloneV transceiver using Custom Phy is needed to perform "running disparity rules" on FPGA logic outside transceiver phy?

I think the answer is yes, but I would to check with experts ;-)

Thank you!

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Are you referring to running disparity checking? If I remember it correct the Custom PHY has this function available where it will flag error when running disparity is incorrect. The output status port is rx_disperr.

  • Altera_Forum's avatar
    Altera_Forum
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    Ok, so I need to transmit control codes on the line and check if extra /R/ is need based on even/odd packet but PCS will check running disparity to perform 8b/10b job.

    e.g., I'm on sync phase and want to transmit data 8'hAA. I will send a /S/ 8'hAA /T/R/R ((tx_paralleldata = 40'hFBAAFDD7D7 ) , tx_datak = 5'b10111)) and then check if rx_disperr still no error. It is correct?

    Cheers!

    ps. I'm not planning auto negotiation for now :)
  • Altera_Forum's avatar
    Altera_Forum
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    Yes, correct. If I test the phy, I monitor rx_runningdisp and rx_errdetect status signals too. Because the running disparity of K28.5 in IDLE code (/I/) must be minus disparity (rx_runningdisp = 1).

    The simple test pattern will be /I/I/I/I/I/I/I/I/S/8'hAA/T/R/R/I/I/I/I/I/I/I/I. rx_disperr and rx_errdetect should be low, and rx_runningdisp should be high when rx_paralleldata = 8'hBC, tx_datak = 1'b1.
  • Altera_Forum's avatar
    Altera_Forum
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    Thank you kkaibara this helps me a lot.

    I will run this test pattern when I write sync state machine. ;-)

    cheers!