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Altera_Forum's avatar
Altera_Forum
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11 years ago

Transceiver PCS Question

When implementing GIGE on CycloneV transceiver using Custom Phy is needed to perform "running disparity rules" on FPGA logic outside transceiver phy? I think the answer is yes, but I would to c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Ok, so I need to transmit control codes on the line and check if extra /R/ is need based on even/odd packet but PCS will check running disparity to perform 8b/10b job.

e.g., I'm on sync phase and want to transmit data 8'hAA. I will send a /S/ 8'hAA /T/R/R ((tx_paralleldata = 40'hFBAAFDD7D7 ) , tx_datak = 5'b10111)) and then check if rx_disperr still no error. It is correct?

Cheers!

ps. I'm not planning auto negotiation for now :)